The traditional fan-out wafer level packaging (FOWLP) generally includes the following steps: first, cutting a single microchip from a wafer, and using a standard pick-and-place device to paste the chip with the front surface facing downwards onto an adhesive layer of a carrier; then forming a plastic encapsulation layer, and embedding the chip into the plastic encapsulation layer; removing the carrier and the adhesive layer after the plastic encapsulation layer is cured, then performing a redistribution layer process and a ball placement reflow process, and finally performing cutting and testing.
A redistribution layer (RDL) is an interface surface between a chip and a package in a flip-chip assembly. The redistribution layer is an extra metal layer that consists of core metal top traces and is used to bind I/O pads of a die outward to other locations such as bump pads. Bumps are usually arranged in a grid pattern with two pads cast on each bump (one on the top and one on the bottom), and the two pads are respectively connected to the redistribution layer and the package substrate.
In the existing fan-out chip packaging technology, the adhesive layer is usually separated from the chip during the process of removing the adhesive layer. However, a part of the adhesive residue may remain inevitably on the chip and the chip is thus contaminated.
There are currently some ways to overcome this drawback. One existing solution is as follows: a redistribution layer is directly formed on a Si supporting wafer, and solder bumps are fabricated on the surface of a semiconductor chip; then the semiconductor chip is adhered to the Si supporting wafer on which the redistribution layer is formed, followed by the formation of a plastic encapsulation layer and the thinning and removal of the Si substrate. This method can effectively prevent the chip contamination problem caused by residue of the adhesive layer. However, since it needs to process the bumps on the surface of the chip prior to chip bonding, and it is difficult to thin and remove the Si substrate, the process complexity is increased. Another existing solution is to form a dielectric layer on the surface of the adhesive layer. This method can overcome the chip contamination problem caused by residue of the adhesive glue and simplify the process steps, but the subsequent formation of through-holes in the dielectric layer is very difficult to achieve.
Therefore, how to provide a chip packaging method to overcome the chip contamination problem caused by the adhesive layer and to simplify the process steps to achieve a good packaging effect has become an important technical problem to be solved urgently by those skilled in the art.